Vivado Design Suite Tool Flow（Vivado Design Suite 工具流程）培训课程

 Vivado Design Suite Tool Flow（Vivado Design Suite 工具流程）培训课程

Who Should Attend?

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite

Course Outline

• Design Methodology Summary
• Project Planning
• Vivado IDE Overview and Projects
• Lab 1: Vivado IDE Projects
• Vivado Tool Flow
• Lab 2: Vivado Tool Flow
• I/O Pin Planning and Clock Constraints
• Lab 3: I/O Pin Planning and Clock Constraints
• ISim Simulator
• Lab 4: XSIM Simulator (VHDL or Verilog)
• Appendix: Design Methodology
• Appendix: HDL Coding Techniques