Essentials of FPGA Design（FPGA设计基础）培训课程
Who should attend?
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs
Course Outline
1
- Design Methodology Summary
- Basic FPGA Architecture
- Introduction to the Vivado Design Suite
- Vivado Design Flows
- Lab 1: Vivado Tool Overview
- Visualization for Analysis
- Designing with IP
- Basic Timing Constraints and Reports
- Lab 2: Vivado Synthesis and Implementation
2
- Designing with FPGA Resources
- Clocking Resources
- Lab 3a: Designing with FPGA Resources
- Lab 3b: Creating an IP Integrator Subsystem Design
- Basic Timing Constraints (XDC)
- Timing Reports
- Lab 4: Basic XDC and Timing Reports
- Synchronous Design Techniques
- FPGA Configuration
- Appendix: SystemVerilog
- Appendix: Design Methodology
- Appendix: HDL Coding Techniques
- Appendix: Using the Pin Planning Environment
